Thermal design methodology for electronic systems

This paper presents the thermal design methodology used to design a multi-processor enterprise server, the RP8400. The proposed methodology combines well-known analytical and experimental thermal design tools, including heat transfer correlations, Flow Network Modeling (FNM) and Computational Fluid Dynamics (CFD) techniques, and experimental measurements. The key benefit of this methodology is its emphasis on the use of varied design tools, each applied at its optimal point in the product design cycle. Thus, analysis time is greatly reduced, with acceptable sacrifice to accuracy and detail, during the earliest stages of design when the design concept is fluid, new ideas abound, and speed is paramount. Detailed analyses, providing a greater degree of accuracy, are performed in the latter stages of the development cycle when designs are firm, changes are fewer, and optimization/validation is the goal. In this manner, thermal risk is systematically reduced throughout the product design cycle. This paper begins with an overview of the thermal design methodology. Direct application of the methodology to the design of an enterprise server, the RP8400, is discussed. Numerical modeling and empirical results are presented and compared, followed by a discussion of methods for improving thermal design in future products

Personal training simulator for asynchronous learning of obstetric ultrasound

To meet the challenges of providing affordable, efficient ultrasound training, a low-cost, portable personal ultrasound training simulator with structured curriculums and integrated assessment methods has been developed. By using extended image volumes for training, the realistic experience of scanning over a larger body surface is emulated

Obstetric Ultrasound Simulator With Task-Based Training and Assessment

The increasing use of point-of-care (POC) ultrasound presents a challenge in providing efficient training to POC ultrasound users for whom formal training is not readily available. In response to this need, we developed an affordable compact laptop-based obstetric ultrasound training simulator. It offers a realistic scanning experience, task-based training, and performance assessment. The position and orientation of the sham transducer are tracked with 5 DoF on an abdomen-sized scan surface with the shape of a cylindrical segment. On the simulator, user interface is rendered a virtual torso whose body surface models the abdomen of the pregnant scan subject. A virtual transducer scans the virtual torso by following the sham transducer movements on the scan surface. A given 3-D training image volume is generated by combining several overlapping 3-D ultrasound sweeps acquired from the pregnant scan subject using a Markov random field-based approach. Obstetric ultrasound training is completed through a series of tasks, guided by the simulator and focused on three aspects: basic medical ultrasound, orientation to obstetric space, and fetal biometry. The scanning performance is automatically evaluated by comparing user-identified anatomical landmarks with reference landmarks preinserted by sonographers. The simulator renders 2-D ultrasound images in real time with 30 frames/s or higher with good image quality; the training procedure follows standard obstetric ultrasound protocol. Thus, for learners without access to formal sonography programs, the simulator is intended to provide structured training in basic obstetrics ultrasound

SIMD Vectorization of Straight Line FFT Code

Abstract. This paper presents compiler technology that targets general purpose microprocessors augmented with SIMD execution units for exploiting data level parallelism. FFT kernels are accelerated by automatically vectorizing blocks of straight line code for processors featuring two-way short vector SIMD extensions like AMD’s 3DNow! and Intel’s SSE 2. Additionally, a special compiler backend is introduced which is able to (i) utilize particular code properties, (ii) generate optimized address computation, and (iii) apply specialized register allocation and instruction scheduling. Experiments show that automatic SIMD vectorization can achieve performance that is comparable to the optimal hand-generated code for FFT kernels. The newly developed methods have been integrated into the codelet generator of Fftw and successfully vectorized complicated code like real-to-halfcomplex non-power-of-two FFT kernels. The floatingpoint performance of Fftw’s scalar version has been more than doubled, resulting in the fastest FFT implementation to date.